Build a RISC-V CPU in VHDL from Scratch

About this course

Design a RISC-V CPU from scratch — and run it on FPGA.This course takes you step by step through the complete design of a RISC-V CPU in VHDL, starting from RISC-V specification and  ending with a fully working System on Chip built around the RISC-V CPU and running C firmware on FPGA.You will start by implementing a RISC-V CPU from scratch, learning how instructions are decoded, executed, and connected to memory at the RTL level. The design then evolves into a complete System-on-Chip, where you will integrate peripherals, define the memory map, and connect hardware to software.A key focus of the course is the hardware–software interface. You will learn how bare-metal software actually works, including stack initialization, linker scripts, startup code, and C firmware integration. To ensure correctness and confidence, the CPU is validated using unit tests and simulations before moving to FPGA.By the end of this course, you will be able to:Design a RISC-V CPU in VHDL from scratchVerify your design with unit tests and simulationBuild and understand a complete RISC-V SoCWrite and run C firmware on your own processorUse linker scripts, stack setup, and startup codeDeploy and test your design on FPGAThis course is ideal for:FPGA and ASIC engineers seeking deep CPU design knowledgeEmbedded software engineers wanting to understand what runs below CStudents aiming to build a strong, differentiating hardware projectAnyone who wants a true end-to-end RISC-V learning experience